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Vol.8, No.2, May 2019. ISSN: 2217-8309 eISSN: 2217-8333
TEM Journal
TECHNOLOGY, EDUCATION, MANAGEMENT, INFORMATICS Association for Information Communication Technology Education and Science |
Design and Simulation of a Nanoscale Threshold-Logic Multiplier
Mawahib Hussein Sulieman, Mariam Mahmoud, Remonda Raafat, Gehad Reda
© 2019 Mawahib Hussein Sulieman, published by UIKTEN. This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License. (CC BY-NC-ND 4.0)
Citation Information: TEM Journal. Volume 8, Issue 2, Pages 333-338, ISSN 2217-8309, DOI: 10.18421/TEM82-03, May 2019.
Received: 08 April 2019.
Abstract:
Multiplication is one of the most important operations in microprocessors and digital signal processing systems. Different multiplier architectures have been proposed in the literature. One of the most widely used architecture is the Wallace tree multiplier. This multiplier is known for its high speed. However, it occupies a large area. In this paper, we used Threshold Logic Gates instead of conventional logic gates to reduce the area. The multiplier was designed in 65nm CMOS technology, and achieved 28% reduction in the number of transistors compared to the one with conventional logic gates. It also achieved a lower power-delay-product.
Keywords – Multiplier, adder, Threshold logic gates. |
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